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FPGA Implementation of Hand-written Number Recognition Based on CNN

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@article{IJASEIT6948,
   author = {Daniele Giardino and Marco Matta and Francesca Silvestri and Sergio Spanò and Valerio Trobiani},
   title = {FPGA Implementation of Hand-written Number Recognition Based on CNN},
   journal = {International Journal on Advanced Science, Engineering and Information Technology},
   volume = {9},
   number = {1},
   year = {2019},
   pages = {167--171},
   keywords = {machine learning; FPGA; accelerator; CNN.},
   abstract = {

Convolutional Neural Networks (CNNs) are the state-of-the-art in computer vision for different purposes such as image and video classification, recommender systems and natural language processing. The connectivity pattern between CNNs neurons is inspired by the structure of the animal visual cortex. In order to allow the processing, they are realized with multiple parallel 2-dimensional FIR filters that convolve the input signal with the learned feature maps.  For this reason, a CNN implementation requires highly parallel computations that cannot be achieved using traditional general-purpose processors, which is why they benefit from a very significant speed-up when mapped and run on Field Programmable Gate Arrays (FPGAs). This is because FPGAs offer the capability to design full customizable hardware architectures, providing high flexibility and the availability of hundreds to thousands of on-chip Digital Signal Processing (DSP) blocks. This paper presents an FPGA implementation of a hand-written number recognition system based on CNN. The system has been characterized in terms of classification accuracy, area, speed, and power consumption. The neural network was implemented on a Xilinx XC7A100T FPGA, and it uses 29.69% of Slice LUTs, 4.42% of slice registers and 52.50% block RAMs. We designed the system using a 9-bit representation that allows for avoiding the use of DSP. For this reason, multipliers are implemented using LUTs. The proposed architecture can be easily scaled on different FPGA devices thank its regularity. CNN can reach a classification accuracy of 90%.

},    issn = {2088-5334},    publisher = {INSIGHT - Indonesian Society for Knowledge and Human Development},    url = {http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=6948},    doi = {10.18517/ijaseit.9.1.6948} }

EndNote

%A Giardino, Daniele
%A Matta, Marco
%A Silvestri, Francesca
%A Spanò, Sergio
%A Trobiani, Valerio
%D 2019
%T FPGA Implementation of Hand-written Number Recognition Based on CNN
%B 2019
%9 machine learning; FPGA; accelerator; CNN.
%! FPGA Implementation of Hand-written Number Recognition Based on CNN
%K machine learning; FPGA; accelerator; CNN.
%X 

Convolutional Neural Networks (CNNs) are the state-of-the-art in computer vision for different purposes such as image and video classification, recommender systems and natural language processing. The connectivity pattern between CNNs neurons is inspired by the structure of the animal visual cortex. In order to allow the processing, they are realized with multiple parallel 2-dimensional FIR filters that convolve the input signal with the learned feature maps.  For this reason, a CNN implementation requires highly parallel computations that cannot be achieved using traditional general-purpose processors, which is why they benefit from a very significant speed-up when mapped and run on Field Programmable Gate Arrays (FPGAs). This is because FPGAs offer the capability to design full customizable hardware architectures, providing high flexibility and the availability of hundreds to thousands of on-chip Digital Signal Processing (DSP) blocks. This paper presents an FPGA implementation of a hand-written number recognition system based on CNN. The system has been characterized in terms of classification accuracy, area, speed, and power consumption. The neural network was implemented on a Xilinx XC7A100T FPGA, and it uses 29.69% of Slice LUTs, 4.42% of slice registers and 52.50% block RAMs. We designed the system using a 9-bit representation that allows for avoiding the use of DSP. For this reason, multipliers are implemented using LUTs. The proposed architecture can be easily scaled on different FPGA devices thank its regularity. CNN can reach a classification accuracy of 90%.

%U http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=6948 %R doi:10.18517/ijaseit.9.1.6948 %J International Journal on Advanced Science, Engineering and Information Technology %V 9 %N 1 %@ 2088-5334

IEEE

Daniele Giardino,Marco Matta,Francesca Silvestri,Sergio Spanò and Valerio Trobiani,"FPGA Implementation of Hand-written Number Recognition Based on CNN," International Journal on Advanced Science, Engineering and Information Technology, vol. 9, no. 1, pp. 167-171, 2019. [Online]. Available: http://dx.doi.org/10.18517/ijaseit.9.1.6948.

RefMan/ProCite (RIS)

TY  - JOUR
AU  - Giardino, Daniele
AU  - Matta, Marco
AU  - Silvestri, Francesca
AU  - Spanò, Sergio
AU  - Trobiani, Valerio
PY  - 2019
TI  - FPGA Implementation of Hand-written Number Recognition Based on CNN
JF  - International Journal on Advanced Science, Engineering and Information Technology; Vol. 9 (2019) No. 1
Y2  - 2019
SP  - 167
EP  - 171
SN  - 2088-5334
PB  - INSIGHT - Indonesian Society for Knowledge and Human Development
KW  - machine learning; FPGA; accelerator; CNN.
N2  - 

Convolutional Neural Networks (CNNs) are the state-of-the-art in computer vision for different purposes such as image and video classification, recommender systems and natural language processing. The connectivity pattern between CNNs neurons is inspired by the structure of the animal visual cortex. In order to allow the processing, they are realized with multiple parallel 2-dimensional FIR filters that convolve the input signal with the learned feature maps.  For this reason, a CNN implementation requires highly parallel computations that cannot be achieved using traditional general-purpose processors, which is why they benefit from a very significant speed-up when mapped and run on Field Programmable Gate Arrays (FPGAs). This is because FPGAs offer the capability to design full customizable hardware architectures, providing high flexibility and the availability of hundreds to thousands of on-chip Digital Signal Processing (DSP) blocks. This paper presents an FPGA implementation of a hand-written number recognition system based on CNN. The system has been characterized in terms of classification accuracy, area, speed, and power consumption. The neural network was implemented on a Xilinx XC7A100T FPGA, and it uses 29.69% of Slice LUTs, 4.42% of slice registers and 52.50% block RAMs. We designed the system using a 9-bit representation that allows for avoiding the use of DSP. For this reason, multipliers are implemented using LUTs. The proposed architecture can be easily scaled on different FPGA devices thank its regularity. CNN can reach a classification accuracy of 90%.

UR - http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=6948 DO - 10.18517/ijaseit.9.1.6948

RefWorks

RT Journal Article
ID 6948
A1 Giardino, Daniele
A1 Matta, Marco
A1 Silvestri, Francesca
A1 Spanò, Sergio
A1 Trobiani, Valerio
T1 FPGA Implementation of Hand-written Number Recognition Based on CNN
JF International Journal on Advanced Science, Engineering and Information Technology
VO 9
IS 1
YR 2019
SP 167
OP 171
SN 2088-5334
PB INSIGHT - Indonesian Society for Knowledge and Human Development
K1 machine learning; FPGA; accelerator; CNN.
AB 

Convolutional Neural Networks (CNNs) are the state-of-the-art in computer vision for different purposes such as image and video classification, recommender systems and natural language processing. The connectivity pattern between CNNs neurons is inspired by the structure of the animal visual cortex. In order to allow the processing, they are realized with multiple parallel 2-dimensional FIR filters that convolve the input signal with the learned feature maps.  For this reason, a CNN implementation requires highly parallel computations that cannot be achieved using traditional general-purpose processors, which is why they benefit from a very significant speed-up when mapped and run on Field Programmable Gate Arrays (FPGAs). This is because FPGAs offer the capability to design full customizable hardware architectures, providing high flexibility and the availability of hundreds to thousands of on-chip Digital Signal Processing (DSP) blocks. This paper presents an FPGA implementation of a hand-written number recognition system based on CNN. The system has been characterized in terms of classification accuracy, area, speed, and power consumption. The neural network was implemented on a Xilinx XC7A100T FPGA, and it uses 29.69% of Slice LUTs, 4.42% of slice registers and 52.50% block RAMs. We designed the system using a 9-bit representation that allows for avoiding the use of DSP. For this reason, multipliers are implemented using LUTs. The proposed architecture can be easily scaled on different FPGA devices thank its regularity. CNN can reach a classification accuracy of 90%.

LK http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=6948 DO - 10.18517/ijaseit.9.1.6948