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An Automatic AW-SOM VHDL IP-core Generator

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@article{IJASEIT9035,
   author = {Daniele Giardino and Marco Matta and Sergio Spanò},
   title = {An Automatic AW-SOM VHDL IP-core Generator},
   journal = {International Journal on Advanced Science, Engineering and Information Technology},
   volume = {9},
   number = {4},
   year = {2019},
   pages = {1136--1141},
   keywords = {clustering; AW-SOM; hardware acceleration; IP generator.},
   abstract = {

In this paper, the authors present a MATLAB IP generator for hardware accelerators of All-Winner Self-Organizing Maps (AW-SOM). AW-SOM is a modified version of Kohonen’s Self Organizing Maps (SOM) algorithm, which is one of the most used Machine Learning algorithms for data clustering, and vector quantization. The architecture of the AW-SOM method is meant for hardware implementations, and its main feature is a processing speed almost independent to the number of neurons since each of them is processed in a parallel way; the parallelization can be easily exploited by hardware custom hardware designs. The IP generator is built-in MATLAB and provides the user with the possibility to design a custom and efficient hardware accelerator. Several settings can be set such as the number of features and the number of neurons. The target language is the VHSIC Hardware Description Language (VHDL). The generated IP cores can be used for the training of the model and a built-in function of the software can also check the clustering performances using its inference capabilities. The accelerators produced by the software have been also characterized in terms of max frequency, hardware resources, and power consumption. The authors performed the hardware implementations on a XILINX Virtex 7 xc7vx690t FPGA.

},    issn = {2088-5334},    publisher = {INSIGHT - Indonesian Society for Knowledge and Human Development},    url = {http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=9035},    doi = {10.18517/ijaseit.9.4.9035} }

EndNote

%A Giardino, Daniele
%A Matta, Marco
%A Spanò, Sergio
%D 2019
%T An Automatic AW-SOM VHDL IP-core Generator
%B 2019
%9 clustering; AW-SOM; hardware acceleration; IP generator.
%! An Automatic AW-SOM VHDL IP-core Generator
%K clustering; AW-SOM; hardware acceleration; IP generator.
%X 

In this paper, the authors present a MATLAB IP generator for hardware accelerators of All-Winner Self-Organizing Maps (AW-SOM). AW-SOM is a modified version of Kohonen’s Self Organizing Maps (SOM) algorithm, which is one of the most used Machine Learning algorithms for data clustering, and vector quantization. The architecture of the AW-SOM method is meant for hardware implementations, and its main feature is a processing speed almost independent to the number of neurons since each of them is processed in a parallel way; the parallelization can be easily exploited by hardware custom hardware designs. The IP generator is built-in MATLAB and provides the user with the possibility to design a custom and efficient hardware accelerator. Several settings can be set such as the number of features and the number of neurons. The target language is the VHSIC Hardware Description Language (VHDL). The generated IP cores can be used for the training of the model and a built-in function of the software can also check the clustering performances using its inference capabilities. The accelerators produced by the software have been also characterized in terms of max frequency, hardware resources, and power consumption. The authors performed the hardware implementations on a XILINX Virtex 7 xc7vx690t FPGA.

%U http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=9035 %R doi:10.18517/ijaseit.9.4.9035 %J International Journal on Advanced Science, Engineering and Information Technology %V 9 %N 4 %@ 2088-5334

IEEE

Daniele Giardino,Marco Matta and Sergio Spanò,"An Automatic AW-SOM VHDL IP-core Generator," International Journal on Advanced Science, Engineering and Information Technology, vol. 9, no. 4, pp. 1136-1141, 2019. [Online]. Available: http://dx.doi.org/10.18517/ijaseit.9.4.9035.

RefMan/ProCite (RIS)

TY  - JOUR
AU  - Giardino, Daniele
AU  - Matta, Marco
AU  - Spanò, Sergio
PY  - 2019
TI  - An Automatic AW-SOM VHDL IP-core Generator
JF  - International Journal on Advanced Science, Engineering and Information Technology; Vol. 9 (2019) No. 4
Y2  - 2019
SP  - 1136
EP  - 1141
SN  - 2088-5334
PB  - INSIGHT - Indonesian Society for Knowledge and Human Development
KW  - clustering; AW-SOM; hardware acceleration; IP generator.
N2  - 

In this paper, the authors present a MATLAB IP generator for hardware accelerators of All-Winner Self-Organizing Maps (AW-SOM). AW-SOM is a modified version of Kohonen’s Self Organizing Maps (SOM) algorithm, which is one of the most used Machine Learning algorithms for data clustering, and vector quantization. The architecture of the AW-SOM method is meant for hardware implementations, and its main feature is a processing speed almost independent to the number of neurons since each of them is processed in a parallel way; the parallelization can be easily exploited by hardware custom hardware designs. The IP generator is built-in MATLAB and provides the user with the possibility to design a custom and efficient hardware accelerator. Several settings can be set such as the number of features and the number of neurons. The target language is the VHSIC Hardware Description Language (VHDL). The generated IP cores can be used for the training of the model and a built-in function of the software can also check the clustering performances using its inference capabilities. The accelerators produced by the software have been also characterized in terms of max frequency, hardware resources, and power consumption. The authors performed the hardware implementations on a XILINX Virtex 7 xc7vx690t FPGA.

UR - http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=9035 DO - 10.18517/ijaseit.9.4.9035

RefWorks

RT Journal Article
ID 9035
A1 Giardino, Daniele
A1 Matta, Marco
A1 Spanò, Sergio
T1 An Automatic AW-SOM VHDL IP-core Generator
JF International Journal on Advanced Science, Engineering and Information Technology
VO 9
IS 4
YR 2019
SP 1136
OP 1141
SN 2088-5334
PB INSIGHT - Indonesian Society for Knowledge and Human Development
K1 clustering; AW-SOM; hardware acceleration; IP generator.
AB 

In this paper, the authors present a MATLAB IP generator for hardware accelerators of All-Winner Self-Organizing Maps (AW-SOM). AW-SOM is a modified version of Kohonen’s Self Organizing Maps (SOM) algorithm, which is one of the most used Machine Learning algorithms for data clustering, and vector quantization. The architecture of the AW-SOM method is meant for hardware implementations, and its main feature is a processing speed almost independent to the number of neurons since each of them is processed in a parallel way; the parallelization can be easily exploited by hardware custom hardware designs. The IP generator is built-in MATLAB and provides the user with the possibility to design a custom and efficient hardware accelerator. Several settings can be set such as the number of features and the number of neurons. The target language is the VHSIC Hardware Description Language (VHDL). The generated IP cores can be used for the training of the model and a built-in function of the software can also check the clustering performances using its inference capabilities. The accelerators produced by the software have been also characterized in terms of max frequency, hardware resources, and power consumption. The authors performed the hardware implementations on a XILINX Virtex 7 xc7vx690t FPGA.

LK http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=9035 DO - 10.18517/ijaseit.9.4.9035