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Fundamental Approach in Digital Circuit Design for 1-MHz Frequency PWM Gate Drive Application

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@article{IJASEIT92,
   author = {Nor Zaihar Yahaya and Mumtaj Begam Raethar and Munirah Khalil and Mohammad Awan},
   title = {Fundamental Approach in Digital Circuit Design for 1-MHz Frequency PWM Gate Drive Application},
   journal = {International Journal on Advanced Science, Engineering and Information Technology},
   volume = {1},
   number = {4},
   year = {2011},
   pages = {453--457},
   keywords = {Duty Ratio; Fixed Time Delay; MOSFET; PWM},
   abstract = {This paper discusses the design of a digital programmable logic circuit to produce a 5 V - output square wave pulses for four high power MOSFET switches using a fixed PWM circuit. It will be applied to drive the synchronous rectifier buck converter(SRBC) circuit. The PWM signals with multiple fixed time delay of 15 ns, 232 ns, 284 ns and 955 ns are generated. The steps taken to analyze each propagation time delay of each logic gate used and its combination are carefully studied. A multiplexer is added at the output of the logic circuit to select and produce the desired output pulses of 20% duty ratio. The logic outputs are compared with the analog pulses and results match each other within 1% in difference.},
   issn = {2088-5334},
   publisher = {INSIGHT - Indonesian Society for Knowledge and Human Development},
   url = {http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=92},
   doi = {10.18517/ijaseit.1.4.92}
}

EndNote

%A Yahaya, Nor Zaihar
%A Raethar, Mumtaj Begam
%A Khalil, Munirah
%A Awan, Mohammad
%D 2011
%T Fundamental Approach in Digital Circuit Design for 1-MHz Frequency PWM Gate Drive Application
%B 2011
%9 Duty Ratio; Fixed Time Delay; MOSFET; PWM
%! Fundamental Approach in Digital Circuit Design for 1-MHz Frequency PWM Gate Drive Application
%K Duty Ratio; Fixed Time Delay; MOSFET; PWM
%X This paper discusses the design of a digital programmable logic circuit to produce a 5 V - output square wave pulses for four high power MOSFET switches using a fixed PWM circuit. It will be applied to drive the synchronous rectifier buck converter(SRBC) circuit. The PWM signals with multiple fixed time delay of 15 ns, 232 ns, 284 ns and 955 ns are generated. The steps taken to analyze each propagation time delay of each logic gate used and its combination are carefully studied. A multiplexer is added at the output of the logic circuit to select and produce the desired output pulses of 20% duty ratio. The logic outputs are compared with the analog pulses and results match each other within 1% in difference.
%U http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=92
%R doi:10.18517/ijaseit.1.4.92
%J International Journal on Advanced Science, Engineering and Information Technology
%V 1
%N 4
%@ 2088-5334

IEEE

Nor Zaihar Yahaya,Mumtaj Begam Raethar,Munirah Khalil and Mohammad Awan,"Fundamental Approach in Digital Circuit Design for 1-MHz Frequency PWM Gate Drive Application," International Journal on Advanced Science, Engineering and Information Technology, vol. 1, no. 4, pp. 453-457, 2011. [Online]. Available: http://dx.doi.org/10.18517/ijaseit.1.4.92.

RefMan/ProCite (RIS)

TY  - JOUR
AU  - Yahaya, Nor Zaihar
AU  - Raethar, Mumtaj Begam
AU  - Khalil, Munirah
AU  - Awan, Mohammad
PY  - 2011
TI  - Fundamental Approach in Digital Circuit Design for 1-MHz Frequency PWM Gate Drive Application
JF  - International Journal on Advanced Science, Engineering and Information Technology; Vol. 1 (2011) No. 4
Y2  - 2011
SP  - 453
EP  - 457
SN  - 2088-5334
PB  - INSIGHT - Indonesian Society for Knowledge and Human Development
KW  - Duty Ratio; Fixed Time Delay; MOSFET; PWM
N2  - This paper discusses the design of a digital programmable logic circuit to produce a 5 V - output square wave pulses for four high power MOSFET switches using a fixed PWM circuit. It will be applied to drive the synchronous rectifier buck converter(SRBC) circuit. The PWM signals with multiple fixed time delay of 15 ns, 232 ns, 284 ns and 955 ns are generated. The steps taken to analyze each propagation time delay of each logic gate used and its combination are carefully studied. A multiplexer is added at the output of the logic circuit to select and produce the desired output pulses of 20% duty ratio. The logic outputs are compared with the analog pulses and results match each other within 1% in difference.
UR  - http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=92
DO  - 10.18517/ijaseit.1.4.92

RefWorks

RT Journal Article
ID 92
A1 Yahaya, Nor Zaihar
A1 Raethar, Mumtaj Begam
A1 Khalil, Munirah
A1 Awan, Mohammad
T1 Fundamental Approach in Digital Circuit Design for 1-MHz Frequency PWM Gate Drive Application
JF International Journal on Advanced Science, Engineering and Information Technology
VO 1
IS 4
YR 2011
SP 453
OP 457
SN 2088-5334
PB INSIGHT - Indonesian Society for Knowledge and Human Development
K1 Duty Ratio; Fixed Time Delay; MOSFET; PWM
AB This paper discusses the design of a digital programmable logic circuit to produce a 5 V - output square wave pulses for four high power MOSFET switches using a fixed PWM circuit. It will be applied to drive the synchronous rectifier buck converter(SRBC) circuit. The PWM signals with multiple fixed time delay of 15 ns, 232 ns, 284 ns and 955 ns are generated. The steps taken to analyze each propagation time delay of each logic gate used and its combination are carefully studied. A multiplexer is added at the output of the logic circuit to select and produce the desired output pulses of 20% duty ratio. The logic outputs are compared with the analog pulses and results match each other within 1% in difference.
LK http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=92
DO  - 10.18517/ijaseit.1.4.92