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A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

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@article{IJASEIT4329,
   author = {Agung Setiabudi and Hiroki Tamura and Koichi Tanno},
   title = {A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit},
   journal = {International Journal on Advanced Science, Engineering and Information Technology},
   volume = {8},
   number = {3},
   year = {2018},
   pages = {924--929},
   keywords = {sample and hold circuit; hold error; hold error reduction; CMOS switch; clock feedthrough; channel charge injection.},
   abstract = {Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width WP range of 3 to 35 µm the average WN/WP ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.},
   issn = {2088-5334},
   publisher = {INSIGHT - Indonesian Society for Knowledge and Human Development},
   url = {http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=4329},
   doi = {10.18517/ijaseit.8.3.4329}
}

EndNote

%A Setiabudi, Agung
%A Tamura, Hiroki
%A Tanno, Koichi
%D 2018
%T A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit
%B 2018
%9 sample and hold circuit; hold error; hold error reduction; CMOS switch; clock feedthrough; channel charge injection.
%! A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit
%K sample and hold circuit; hold error; hold error reduction; CMOS switch; clock feedthrough; channel charge injection.
%X Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width WP range of 3 to 35 µm the average WN/WP ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.
%U http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=4329
%R doi:10.18517/ijaseit.8.3.4329
%J International Journal on Advanced Science, Engineering and Information Technology
%V 8
%N 3
%@ 2088-5334

IEEE

Agung Setiabudi,Hiroki Tamura and Koichi Tanno,"A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit," International Journal on Advanced Science, Engineering and Information Technology, vol. 8, no. 3, pp. 924-929, 2018. [Online]. Available: http://dx.doi.org/10.18517/ijaseit.8.3.4329.

RefMan/ProCite (RIS)

TY  - JOUR
AU  - Setiabudi, Agung
AU  - Tamura, Hiroki
AU  - Tanno, Koichi
PY  - 2018
TI  - A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit
JF  - International Journal on Advanced Science, Engineering and Information Technology; Vol. 8 (2018) No. 3
Y2  - 2018
SP  - 924
EP  - 929
SN  - 2088-5334
PB  - INSIGHT - Indonesian Society for Knowledge and Human Development
KW  - sample and hold circuit; hold error; hold error reduction; CMOS switch; clock feedthrough; channel charge injection.
N2  - Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width WP range of 3 to 35 µm the average WN/WP ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.
UR  - http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=4329
DO  - 10.18517/ijaseit.8.3.4329

RefWorks

RT Journal Article
ID 4329
A1 Setiabudi, Agung
A1 Tamura, Hiroki
A1 Tanno, Koichi
T1 A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit
JF International Journal on Advanced Science, Engineering and Information Technology
VO 8
IS 3
YR 2018
SP 924
OP 929
SN 2088-5334
PB INSIGHT - Indonesian Society for Knowledge and Human Development
K1 sample and hold circuit; hold error; hold error reduction; CMOS switch; clock feedthrough; channel charge injection.
AB Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width WP range of 3 to 35 µm the average WN/WP ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.
LK http://ijaseit.insightsociety.org/index.php?option=com_content&view=article&id=9&Itemid=1&article_id=4329
DO  - 10.18517/ijaseit.8.3.4329