DOI : https://doi.org/10.18517/ijaseit.14.2.18504

FPGA Implementation of a Pipelined Kalman Filter for Object Tracking in Two Dimensions

Jonghuy Choi (1), Yonghyeok Yoon (2), Taekyeong Song (3), Sunhee Kim (4)
(1) Department of System Semiconductor Engineering, Sangmyung University, 31, Sangmyeongdae-gil, Dongnam-gu, Cheonan-si, Chungcheongnam-do,31066, Republic of Korea
(2) Department of System Semiconductor Engineering, Sangmyung University, 31, Sangmyeongdae-gil, Dongnam-gu, Cheonan-si, Chungcheongnam-do,31066, Republic of Korea
(3) Department of System Semiconductor Engineering, Sangmyung University, 31, Sangmyeongdae-gil, Dongnam-gu, Cheonan-si, Chungcheongnam-do,31066, Republic of Korea
(4) Department of System Semiconductor Engineering, Sangmyung University, 31, Sangmyeongdae-gil, Dongnam-gu, Cheonan-si, Chungcheongnam-do,31066, Republic of Korea
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How to cite (IJASEIT) :
Choi, Jonghuy, et al. “FPGA Implementation of a Pipelined Kalman Filter for Object Tracking in Two Dimensions”. International Journal on Advanced Science, Engineering and Information Technology, vol. 14, no. 2, Apr. 2024, pp. 540-7, doi:10.18517/ijaseit.14.2.18504.
Citation Format :
In a location tracking system for a moving object, not only accuracy but also real-time processing are important factors. The Kalman filter, as a recursive function, stands out as one of the prominent algorithms for object tracking. It continuously compares measured data with predicted values based on the system characteristics in real time, and then corrects the error of the predicted values while considering the noise of both system and measured data. This paper focuses on designing a hardware-based Kalman filter for object tracking in two dimensions. Following an analysis of the Kalman filter algorithm, the blocks capable of parallel processing are identified and configured to be processed in parallel, effectively reducing data processing time. The clock speed is enhanced by using the pipeline technique. In addition, the time-sharing technique is applied to increase the utilization of hardware resources and reduce the area. Data was processed at 32-bit floating points to uphold accuracy comparable to software-implemented Kalman filters. The proposed Kalman filter architecture is designed using verilog HDL and then simulated in Synopsys VCS/Verdi. And the accuracy is verified by comparing results with a software-based Kalman filter designed using MATLAB. It was implemented using Zynq ZYNQ-7 ZC702 Programmable logic via Xilnix Vivado, and can operate at 33MHz. It takes a total of 44 clocks, or 1.32 us, to process one data. Therefore, it was confirmed that the designed Kalman filter hardware is suitable for real-time processing.

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