DOI : https://doi.org/10.18517/ijaseit.14.6.10066

Power-efficient 4-bit 40-MS/s Time-domain 2-times Interpolating Flash ADC Using Complementary Latching Technique

Beomjin Kim (1), Dongryeol Oh (2)
(1) Department of Electronic Engineering Jeju National University, 102, Jejudaehak-ro, Jeju-si, Jeju-do, Republic of Korea
(2) Department of Electronic Engineering Jeju National University, 102, Jejudaehak-ro, Jeju-si, Jeju-do, Republic of Korea
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How to cite (IJASEIT) :
Kim , Beomjin, and Dongryeol Oh. “Power-Efficient 4-Bit 40-MS S Time-Domain 2-Times Interpolating Flash ADC Using Complementary Latching Technique”. International Journal on Advanced Science, Engineering and Information Technology, vol. 14, no. 6, Dec. 2024, pp. 1906-13, doi:10.18517/ijaseit.14.6.10066.
Citation Format :
We propose a power-efficient 4-bit 40-MS/s 2-times time-domain interpolating flash analog-to-digital converter (ADC) using complementary dynamic amplifiers (CDAs). The flash ADC can be utilized for high-speed data conversion. However, as the resolution of a conventional flash ADC increases, the number of comparators grows, resulting in greater area and higher power consumption. To address these drawbacks, we propose a comparator structure consisting of one CDA, two types of latches, and a 2-times time-domain interpolation technique using these CDAs. The CDA can amplify twice in one clock cycle, reducing the design burdens such as power consumption, high-speed clock drivers, and high-speed dynamic latches compared to the conventional dynamic amplifier (DA)-based flash ADC. A CDA-based time-domain interpolation technique is also applied to improve power and area efficiencies in the proposed flash ADC. The prototype ADC was fabricated using a 500 nm CMOS process (2-poly, 3-metal). Thanks to the power-efficient CDA and time-domain interpolation technique, the power efficiency of the proposed ADC can be improved by 42% compared to the DA-based flash ADC. The measured differential non-linearity (DNL) and integral non-linearity (INL) are -0.29/+0.17 LSB and -0.00/+0.30 LSB, respectively. The measured spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) at Nyquist input frequency are 36.63 dB and 24.21 dB, respectively, with a power consumption of 91 mW, and the figure of merit (FoM) is 172.6 pJ/conversion-step.

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