DOI : https://doi.org/10.18517/ijaseit.8.3.4329

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

Agung Setiabudi (1), Hiroki Tamura (2), Koichi Tanno (3)
(1) University of Miyazaki
(2) University of Miyazaki
(3) University of Miyazaki
Fulltext View | Download
How to cite (IJASEIT) :
Setiabudi, Agung, et al. “A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S H Circuit”. International Journal on Advanced Science, Engineering and Information Technology, vol. 8, no. 3, June 2018, pp. 924-9, doi:10.18517/ijaseit.8.3.4329.
Citation Format :
Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width WP range of 3 to 35 µm the average WN/WP ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.

Y. Fan, Y. Huijing and L. Gang, “A 4th-order Switch-capacitor Low-pass Filter for Quartz Gyroscope Interface Circuit,” TELKOMNIKA, Vol. 11, No. 10, pp. 5718-5724, 2013.

Y. Fan, Y. Huijing and L. Gang, “A High-Performance Sigma-Delta ADC for Audio Decoder Chip,” TELKOMNIKA, Vol. 11, No. 11, pp. 6570-6576, 2013.

B.J. Sheu, J.H. Shieh, and M. Patil, “Modeling charge injection in MOS analog switches,” IEEE Transactions on Circuits and Systems, vol. CAS-34, no. 2, pp. 214-216, 1987.

B.J. Sheu and C. Hu, “Switch-induced error voltage on a switched capacitor,” IEEE Journal of Solid-State circuits, vol. SC-19, no. 4, pp. 519-525, 1984.

G. Wegmann and E. Vittoz, and F. Rahali, “Charge injection in analog MOS switches,” IEEE Journal of Solid-State Circuits, vol. SC-22, no. 6, pp. 1091-1097, 1987.

J.H. Shieh, M. Patil, and B J. Sheu, “Measurement and analysis of charge injection in MOS analog switches,” IEEE J. Solid-State Circuits, vol. SC-22, no. 2, pp. 277-281, Apr. 1987.

Y.B. Gu and M.J. Chen, “A new quantitative model for weak inversion charge injection in MOSFET analog switches,” IEEE Transactions on Electron Devices, vol. 43, no. 2, pp. 295-301, 1996.

A. Danchiv, M. Bodea, “A New Simplified Model for Charge Injection Induced Sample and Hold Error,” 15th IEEE Mediterranean Electrotechnical Conference MELECON 2010, pp.743-748. 2010.

P. Torkzadeh and M. Atarodi, “Channel Charge Injection analysis and its modeling in z-domain for switched-capacitor integrators,” 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, Cancun, pp. 126-129, 2009.

P. Torkzadeh, M. Atoradi, “Behavioral Modeling of Clock Feed-Through and Channel Charge Injection NonIdeal Effects in SIMULINK for Switched-Capacitor Integrator,” Elsevier Simulation Modelling Practice and Theory 18, pp.483-499, 2009.

W. Xu, G. Friedman, “Clock Feedthrough in CMOS Analog Transmission Gate Switches,” Springer Analog Integrated Circuits and Signal Processing, 44, 271-281, 2005.

B. Razavi, “Design of analog CMOS integrated circuits,” McGraw-Hill, 2001.

R. C. Yen, P. R. Gray, “A MOS switched-capacitor instrumentation amplifier,” IEEE Journal of Solid-State Circuits, 17 (6), pp. 1008-1013, 1982.

A. Abolhasani, M. Tohidi, K. Hadidi, A. Khoei, “A new high-speed, high-resolution open-loop CMOS sample and hold,” Analog Integrated Circuits and Signal Processing, 78 (2), pp. 409-419, 2014.

T. Moradi Khanshan, M. Nematzade, K. Hadidi, A. Khoei, Z. D. Koozehkanani, J. Sobhi, “Very linear open-loop CMOS sample-and-hold structure for high precision and high-speed ADCs,” Analog Integrated Circuits and Signal Processing, 88 (1), pp. 23-30, 2016.

M. Mousazadeh, “A highly linear open-loop high-speed CMOS sample and hold,” Analog Integrated Circuits and Signal Processing, 90 (3), pp. 703-710, 2017.

T. Nonthaputha, M. Kumngern, S. Lerkvaranyu, “CMOS sample-and-hold circuit using current conveyor analog switch,” in 2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 1-4, 2016.

L. Mountrichas, S. Siskos, “A high-speed offset canceling distributed sample-and-hold architecture for flash A/D converters,” Microelectronics Journal, 44 (12), pp. 1123-1131, 2013.

K. Ding, K. Cai, Y. Han, “Design of a high-speed sample-and-hold circuit using a substrate-biasing-effect attenuated T switch,” Microelectronics Journal, 41 (12), pp. 809-814, 2010

P. Pouya, A. Ghasemi, H. Aminzadeh, “A low-voltage high-speed high linearity MOSFET-only analog bootstrapped switch for sample-and-hold circuits,” in 2015 2nd International Conference on Knowledge-Based Engineering and Innovation (KBEI), pp. 418-421, 2015.

T. B. Nazzal, S. A. Mahmoud, “Low-power bootstrapped sample and hold circuit for analog-to-digital converters, in: 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, 2016.

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

Authors who publish with this journal agree to the following terms:

    1. Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
    2. Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
    3. Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See The Effect of Open Access).