DOI : https://doi.org/10.18517/ijaseit.15.2.12515

Design and Implementation of Four-Parallel Turbo Decoder for HomePlug Green PHY

Jeongju Jeon (1), Sunhee Kim (2)
(1) Department of System Semiconductor Engineering, Sangmyung University, Cheonan-si, Chungcheongnam-do, Republic of Korea
(2) Department of System Semiconductor Engineering, Sangmyung University, Cheonan-si, Chungcheongnam-do, Republic of Korea
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J. Jeon and S. Kim, “Design and Implementation of Four-Parallel Turbo Decoder for HomePlug Green PHY”, Int. J. Adv. Sci. Eng. Inf. Technol., vol. 15, no. 2, pp. 464–470, Apr. 2025.
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As electric vehicles are popularized, the importance of the safety of electric vehicle batteries has increased. Lithium-ion batteries, which are mainly used as batteries for electric vehicles, have the possibility of fire due to thermal factors, collisions, and overcharging. Recently, to prevent overcharging, battery information is exchanged between electric vehicle chargers and electric vehicle battery management systems using PLC. HomePlug Green Phy(HPGP) is a communication method for Smart Grid applications and EVs among PLCs. HPGP uses 3072-OFDM, and the number of available carriers varies depending on the region. One PHY block is generated with several to dozens of OFDM symbols. Therefore, to guarantee a constant latency of the PHY transceiver, a high-speed transceiver that can process FEC within the required time is needed. In this paper, we propose a 4-parallel turbo decoder. By analyzing channel interleaver for HPGP, four turbo decoders can be processed simultaneously. Through analysis of the turbo interleaving/deinterleaving address, the turbo decoder shares the data memory of the channel deinterleaver. It reduces the interleaving/deinterleaving address memory size, thereby reducing the overall memory size. The proposed architecture was designed with Verilog, and its functions were verified using VCS/Verdi. The Kintex UltraScale Xcku11p-ffve1517-2-e was used as the target for implementation. The clock frequency is 125 MHz. After analyzing the overall architecture of HPGP FEC, the design was made considering the timing and interface with the pre/post blocks of the Encoder and Decoder, so it will be well used in the HPGP transceiver.

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